Control of current in an inductance with pulse width modulation at control frequency

ABSTRACT

A PWM controller for a bridge driver circuit for controlling current in an inductive load such as a motor, can set the driver into a forward mode, a slow decay mode or a fast decay mode, and can switch from slow decay mode into forward mode or into fast decay mode for the duration of pulses at controlled time intervals to provide pulse width modulated control of the current. This is a simpler control scheme avoiding complex switching schemes related to mixed mode decay. By using a controlled PWM frequency, it is easier to avoid the problems of variable frequency such as increased heat dissipation or acoustic noise generation. It can have a selector for selecting top or bottom sense switching, enabling a wider range of stable PWM duty-cycles to be used (e.g. 0% to 100%), which is useful to compensate for Back emf influence on coil-drive.

THE FIELD OF THE INVENTION

This application claims priority under 35 U.S.C. 119 to patentapplication number 0317629.4 filed in the United Kingdom on Jul. 28,2003, which is incorporated by reference herein in its entirety.

BACKGROUND OF THE INVENTION

1. Cross-Reference to Related Applications

This invention relates to controllers for controlling current in aninductive load, to integrated circuits or systems having suchcontrollers and to corresponding methods.

2. Background and Relevant Art

It is known to control current in an inductive load (such as a coil, asolenoid and a motor winding) by means of Pulse Width Modulation (PWM)and driver transistors in a full-bridge configuration. Based onmeasurements of the coil current, a controller executes a decisionprocess to determine when to switch the drivers. A coil current sensorcircuit is used to measure the coil current and feed back a measure ofthe coil current. This value is compared to a reference signalindicating a desired current, to produce a current error signal. Thecontroller alters the timing of the switching dynamically to minimizethe error signal. Typically the drivers are arranged as an H bridge toenable a DC supply voltage to be switched to drive the coil alternatelywith positive and negative voltages. Such drivers have a number ofdriving modes as follows: forward (also known as charge mode, with apositive drive voltage), fast decay (with a negative drive voltage) andslow decay (also called freewheel, with no drive voltage, but with thecoil short circuited to allow the induced current to flow and decay).These modes are switched at different times to provide pulse widthmodulated control. The waveform of each pulse can be varied by using amixture of the three modes within a single cycle of the PWM. This isshown as a mixed decay mode.

FIGS. 1, 2 and 3 show a current flow through a known H bridge in forwardmode, slow decay mode and fast decay mode respectively. The H bridge hastransistors U1, L1 coupled in series between the supply lines Vm andPGND and transistors U2, L2 are likewise coupled in series. Parasiticdiodes are shown with dotted lines across each transistor. The inductiveload, e.g. a coil, is connected across the mid points of the transistorpairs UI-L1, U2-L2. In the forward mode shown in FIG. 1, transistors UIand L2 are on and transistors U2 and L1 are off, so the current flowsfrom supply line Vm through transistor UI then the inductive load, herea coil, then transistor L2 and to supply line PGND. In the slow decaymode shown in FIG. 2, transistors UI and U2 are off and transistors LIand L2 are on so the current flows from the coil or inductive loadthrough transistor L2 to supply line PGND, to transistor L1 and back tothe coil or inductive load. In the fast decay mode shown in FIG. 3,transistors UI and L2 are off and transistors L1 and U2 are on so thecurrent flows from supply line PGND to transistor LI to the coil orinductive load, to transistor U2, then to supply line Vm. Many differentways of controlling the switching of the drivers for switching thetransistors UI, U2, L1, L2 to control the coil current are known.

For example, the switching can be carried out at a fixed frequency orvariable frequency. One variable frequency method is called peak currentcontrol with fixed off time. This involves switching into freewheel orslow decay mode for a fixed time interval, and then driving the coil orinductive load until the current reaches the desired reference value. Inthis case the driving period varies and so the switching frequencyvaries. This is also called top sensing since switching occurs to makethe top of the pulses match the desired current level. Another method ispeak current control with fixed frequency. In this case, the freewheeltime is not fixed, but the total of drive time and freewheel time isfixed, so the switching has a fixed frequency. It is also known to havemean value control to address the issue that peak control gives a meanoutput which is always lower than the reference current.

One known controller is the Allegro 3977 integrated circuit (IC). Ituses a mixed decay mode with fixed off-time in its PWM currentregulators, which limits the load current to a desired value. Initially,a diagonal pair of source and sink transistors are enabled and currentflows through the inductive load as shown in FIG. 1. When the loadcurrent has the desired value, a current-sense comparator resets the PWMlatch, which turns off both the source and the sink transistors in orderto obtain mixed decay mode, and the current recirculates as in FIGS. 2and 3. During this recirculation the current decreases until the fixedoff-time expires. Mixed decay splits the fixed off-time of the PWM cycleinto fast and then slow decay. After the fixed off-time of the PWMcycle, the appropriate transistors are enabled again, the inductive loadcurrent increases and the PWM cycle is repeated. Using mixed decay withfixed off-time has the advantage that PWM frequency is variable (lowerpeak in EMC spectrum, because energy in spectrum is smeared), but itneeds relatively high frequency to guarantee operation above 20 kHz andthis generates additional heat-losses. There are also externalcomponents involved, which adds to the cost and complexity. This priorart, which shows current-control with non-constant frequency PWM has thepotential effect that PWM frequency could drop below 20 kHz (commonlyused as an acceptable audible limit). The frequency variation is relatedto PWM generation of the current-control block that depends oncoil-inductance, supply voltage, motor speed, current levels and otherparameters. This can cause audible noise and related human discomfort.

Another known controller is the Infineon TLE-472x series ICs. These usea fixed frequency chopper with forward drive and brake (=slow decay)mode. Current-switching is top-sensing only. This known deviceapparently does not use a fast decay mode. Draw-backs of this includeslow reaction time in certain motor load conditions and speeds: PWM dutycycle will be less than 50%.

Another known device is the Toshiba TB62200. This uses fixed frequencyPWM with slow, fast and mixed decay. Using mixed decay mode, whichrequires additional switching points involves increased complexity.There is no indication of using other than top sensing.

U.S. Pat. No. 5,428,522 shows a four quadrant unipolar pulse widthmodulated (PWM) power conversion circuit for supplying a desired currentto an inductive load such as a motor. The power conversion circuit usesan H-bridge circuit topology having an upper pair and lower pair ofswitching elements wherein the load is connected across a positivepotential and negative potential DC power source. Diodes in parallelwith each of the switching elements provide a current path from the loadto the power source when its respective switching element isnon-conductive. The value of the load current is compared to a desiredload current value and switching element control signals are generatedin accordance with a control algorithm to cause the instantaneousvoltage across the load to alternate between a single polarity voltageand zero for a portion of the output load waveform to cause the averagevalue of the load current to correspond generally with the desiredaverage load current.

U.S. Pat. No. 4,757,241 is concerned with the problem that PWM systemswhich regulate current have required continuous monitoring of loadcurrent to avoid uncontrolled high frequency switching, or haveexhibited discontinuity in control output when load current approachesthe regulated value, or have not provided for a smooth transition from acurrent control mode to a voltage control mode. Two known methods toaddress this employ either a free-running oscillator to establish afixed maximum frequency of operation or a monostable timer to establisha fixed off time. Each of these circuits have their advantages anddisadvantages. To overcome the disadvantages, a logic means limits thecycling of the PWM enable signal to once per clock interval, and ifdesired, the logic means can establish a minimum time period during eachclock interval in which the PWM enable signal may be inhibited in orderto provide a minimum OFF interval for current decay in each cycle.

BRIEF SUMMARY OF THE INVENTION

According to a first aspect, the invention provides: a controller for abridge driver circuit for pulse width modulated control of a current inan inductive load, the controller being arranged to set the driver intoa forward mode, a slow decay mode or a fast decay mode, and beingarranged to switch from slow decay mode into forward mode or into fastdecay mode for the duration of pulses at controlled time intervals toprovide pulse width modulated control of the current.

This can offer a simpler control scheme with lower complexity bymultiplexing forward mode and fast decay mode over different PWM periodsand thus avoiding complex switching schemes related to mixed mode decay.By imposing a controlled frequency, it is easier to avoid the problemsof weakly controlled PWM frequency such as increased heat dissipation oracoustic noise generation.

As additional features, the controller can have a selector for selectingtop or bottom sense switching. This is notable for enabling a widerrange of PWM duty-cycles to be used (e.g. 0% to 100%), which is usefulto compensate for Back emf (Bemf) influence on coil-drive.

Another such feature is this selector being arranged to select accordingto a duty cycle or mark space ratio of an output of the controller. Thisenables output instability to be detected, such as that caused bychanges in back emf. This can employ a simple detector circuit fordetecting when the duty cycle or mark space ratio reaches apre-determined value between 0.5 and 1, e.g. 0.75, and using this tomake the selection. The selector for selecting top or bottom senseswitching may have an instability sampling point anywhere between 50%and 100% of the duty cycle. The position is a compromise between fastreaction time (switching when the ratio is just above 50%, or thus thevalue is just above 0.5) and stable operation on noisy environment(switching when the ratio is about 100%, or thus the value is almost andup to 1).

Another additional feature is a current sensor in the load coupled toprovide feedback to the controller.

Another such feature is a latch for outputting a drive control signal,the latch being set by a clock signal and reset by a signal indicatingthe coil current has reached a desired level.

Another such feature is the controller being arranged to delay aswitching of the bridge driver to provide a guard band to avoid anoverlap between modes which could lead to a brief short circuit.

Another aspect of the invention provides a pulse width modulationcontroller for pulse width modulated controlling of current in aninductive load according to a comparison of a desired and a measuredcurrent, the controller being arranged to carry out top sensing wherefor each pulse, the current is driven up until it reaches the desiredvalue, after which it is allowed to decay or to carry out a bottomsensing where for each pulse, the current is driven away from thedesired value and allowed to decay towards the desired value, thecontroller having a selector for selecting top or bottom senseswitching. As discussed above, this is notable for enabling a widerrange of PWM duty-cycles to be used (e.g. 0% to 100%), which is usefulto compensate for back emf influence on coil-drive. The selector can bearranged to select according to a duty cycle or mark space ratio of anoutput of the controller. This enables output instability to bedetected, such as that caused by changes in back emf. This can employ asimple circuit for detecting when the duty cycle or mark space ratioreaches a pre-determined value between 0.5 and 1, e.g. 0.75.

The embodiments of the invention using some or all of the above featureshave a number of advantages:

1) PWM frequency is fully controlled by means of a clock signal, suchthat audible noise and overheating can be avoided in all operatingconditions. There are no other components needed to tune the PWMfrequency to motor parameters and operating conditions.

2) All PWM duty-cycles can be reached (0% to 100%), which is importantto compensate Bemf influence on coil-drive.

3) PWM generation is simple as it does not implement mixed decay mode.It uses only slow or fast decay mode per PWM period. There are noadditional switching points per PWM period necessary, so no additionalhardware is required to control and generate the switching point betweenfast and slow decay.

Other aspects of the invention include an integrated circuitincorporating the controller.

Another aspect provides a system having the controller, and a motor asthe inductive load controlled by the controller. As the advantages feedthrough to add value to the system as a whole, it is useful to claim thesystem explicitly.

Other aspects include corresponding methods of controlling a current inan inductive load.

A method of controlling a current in an inductive load by switchingbetween a forward mode, a slow decay mode or a fast decay mode accordingto the present invention comprises switching from slow decay mode intoforward mode or into fast decay mode for the duration of pulses atcontrolled time intervals to provide pulse width modulated control ofthe current. This offers a simpler control scheme with lower complexityby multiplexing forward mode and fast or slow decay mode over differentPWM periods and thus avoiding complex switching schemes related to mixedmode decay.

A method according to the present invention may furthermore compriseselecting top or bottom sense switching. Selecting top or bottom senseswitching may be done according to a duty cycle of an output of thecontroller. A method according to the present invention may furthermorecomprise detecting when the duty cycle reaches a pre-determined valuebetween 0.5 and 1, e.g. 0.75, and use this to select top or bottom senseswitching.

A method according to the present invention may furthermore comprisesensing a current in the inductive load to provide feedback control.

A drive control signal may be output, which drive control signal is setby a clock signal and is reset by a signal indicating a current in theinductive load has reached a desired level.

Switching between a forward mode, a slow decay mode or a fast decay modemay be delayed to provide a guard band to avoid an overlap betweenmodes.

In a further aspect, the present invention provides a method ofcontrolling a current in an inductive load by pulse width modulationaccording to a comparison of a desired and a measured current. Themethod comprises selecting between top sensing where for each pulse thecurrent is driven up until it reaches a desired value after which it isallowed to decay, or bottom sensing where for each pulse the current isdriven away from the desired value and allowed to decay towards thedesired value. Selecting may be arranged according to a duty cycle of anoutput of a controller controlling the current in the inductive load.

How the present invention may be put into effect will now be describedwith reference to the appended schematic drawings. Obviously, numerousvariations and modifications can be made without departing from theclaims of the present invention. Therefore, it should be clearlyunderstood that the form of the present invention is illustrative onlyand is not intended to limit the scope of the present invention

BRIEF DESCRIPTION OF THE DRAWINGS

The features of the invention will be better understood by reference tothe accompanying drawings, which illustrate preferred embodiments of theinvention. In the drawings:

FIGS. 1 to 3 show a prior art bridge driver and current flows in forwardmode, in slow decay mode and in fast decay mode respectively,

FIG. 4 shows a controller according to a first embodiment of theinvention in the form of a circuit for generating rise and fall pulsesfor the forward and fast decay modes respectively,

FIG. 5 shows a graph of the operation of the circuit of FIG. 4,

FIG. 6 shows a controller according to a second embodiment of theinvention having a circuit for selecting between top sensing and bottomsensing, and

FIG. 7 shows a graph of the operation of the circuit of FIG. 6.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention will be described with respect to particularembodiments and with reference to certain drawings but the invention isnot limited thereto but only by the claims. The drawings described areonly schematic and are non-limiting. In the drawings, the size of someof the elements may be exaggerated and not drawn on scale forillustrative purposes.

The terms first, second, third and the like in the description and inthe claims, are used for distinguishing between similar elements and notnecessarily for describing a sequential or chronological order. It is tobe understood that the terms so used are interchangeable underappropriate circumstances and that the embodiments of the inventiondescribed herein are capable of operation in other sequences thandescribed or illustrated herein.

A useful discussion of PWM control of inductive loads such as motors canbe found in “Power Electronics and Variable Frequency Drives”, ed. B. K.Bose, IEEE press, 1997, especially chapter 4. Reference is made below tologic circuits. A useful discussion of logic circuits can be found in“Digital Logic Design”, B. Holdsworth and C. Woods, Newnes, 2002.

A term often used in PWM control is “Duty cycle” or “mark space ratio”.This is a number that varies between 0 and 1 (or for example between 0%and 100%). It is the ratio of “active PWM signal”=“PWM signal high” andthe PWM signal's period or in other words: T_(on)/T_(pwm) period.

FIGS. 4, 5: Four Quadrant Controller

FIG. 4 shows a controller 40 according to an embodiment of theinvention. The controller 40 makes decisions based on the comparisonV_(err) of the value of a measured current I_(coil) in an inductiveload, e.g. a coil-current, with the value of a desired coil-currentI_(Req). Using any suitable current sensing circuit (e.g. the voltagedrop over a resistor in series with the coil) in combination with acomparator 41, a compare signal CMP is generated (FIG. 4). The circuitalso takes in a clock signal Clk and outputs logic signals PTON, NTON,PBON, NBON for driving 4 logic circuits of a bridge. The signal CMPindicates whether the current regulation error Verr is positive ornegative. This is latched by a latch circuit 42, e.g. a D-type latchclocked by the clock signal Clk on the clock input. In the D type latch42, when the CLK input is logic 1, the Q output will always reflect thelogic level present at the D input, no matter how that changes. When theCLK input falls to logic 0, the last state of the D input is trapped andheld in the latch, for use by the subsequent circuit that needs thissignal.

The latched output Q and its inverse !Q are fed to a pair of set/resetdevices 43, 44 which output a fall signal Fall and a rise signal Riserespectively. To achieve this, the positive output Q of the latchcircuit 42 is preferably NANDed with the comparator output CMP andapplied to the reset input R of a first set/reset device 43. The setinput S of this first set/reset device 43 is the positive output Q ofthe latch circuit 42 ANDed with the clock signal Clk. The reset input Rof the second set/reset device 44 is the inverted output !Q of the latchcircuit 42 NANDed with the inverse of the comparator output CMP. The setinput S of the second set/reset device 44 is the inverted output !Q ofthe latch circuit 42 ANDed with the clock signal Clk.

The circuit functions as follows. When the measured coil currentI_(coil) is larger than the desired coil current I_(Req), the comparatorsignal CMP is positive, and a logic 1 is applied to the D input of thelatch circuit 42. The output Q of the latch circuit 41 follows the Dinput, and during a 0 clock signal Clk, the state of the D input istrapped, in this case a logic 1. This means that the output Q of thefirst set/reset device 43 will be at a logic 1 as well, and that a fallsignal Fall with a logic 1 will be generated. At the same time, theoutput Q of the second set/reset device 44 is at a logic 0, and a risesignal Rise with a logic 0 will be generated. On the other hand, whenthe measured coil current I_(coil) is smaller than the desired coilcurrent I_(Req), the comparator signal CMP is negative, and a logic 0 isapplied to the D input of the latch circuit 42. The output Q of thelatch circuit 41 follows the D input, and during a 0 clock signal Clk,the state of the D input is trapped, in this case a logic 0. This meansthat the output Q of the first set/reset device 43 will be at a logic 0as well, and that a fall signal Fall with a logic 0 will be generated.At the same time, the output Q of the second set/reset device 44 is at alogic 1, and a rise signal Rise with a logic 1 will be generated.

The Rise signal and an inverted Rise signal are each fed through a delaydevice 45, 46 to delay a leading edge, to achieve a dead band or guardband, then output as PTON and PBON respectively. The Fall signal and aninverted Fall signal are each fed through a delay device 47, 48 to delaya leading edge, to achieve a dead band or guard band, then output asNTON and NBON respectively. In the first case, the measured coil currentI_(coil) being larger than the desired coil current I_(Req) at a certainpulse of the clock signal Clk, the coil current is driven so as todecrease. At the moment both currents I_(coil) and I_(Req) become equal,possibly between two pulses of the clock signal Clk, the Fall signalfalls back to logic zero, and the measured coil current, not beingdriven to decrease, automatically increases again. In the second case,the measured coil current I_(coil) being smaller than the desired coilcurrent I_(Req), at a certain pulse of the clock signal Clk, the coilcurrent is driven so M to increase. At the moment both currents I_(coil)and I_(Req) become equal, possibly between two pulses of the clocksignal Clk, the Rise signal falls back to logic zero, and the measuredcoil current, not being driven to increase, automatically decreasesagain.

As shown in the graph of FIG. 5, the Rise and Fall signals are pulsed atvarying widths to drive the coil current I_(coil) up or down to matchthe requested current I_(Req). These are the forward and fast decaymodes as shown in FIGS. 1 and 3. In between the pulses, when neither theRise nor the Fall signals are present, the driver is in the slow decaymode of FIG. 2. This shows 4 quadrant current control with automaticselection of Rise or Fall once per clock cycle, to achieve theadvantages set out above.

FIGS. 6 7 Top: and Bottom Sensing Selection

FIG. 6 shows another embodiment of the invention in the form of acontroller 60 having a digital logic circuit 61 for achieving morestable control over a wider range of duty cycles. It has automaticselection of top sensing or bottom sensing control. It is shown forcontrolling one pair of switches 62, 63, e.g. transistors, but can beapplied equally to the 4 quadrant case of FIG. 4. It has the PWM clockand a voltage I_(req) indicating the required current as inputs. Asingle output Out is used in inverted and non-inverted forms to drivethe pair of switches 62, 63, e.g. transistors, used to drive the loadL_(load). A sense resistor R_(sense) is coupled in the path of the coilcurrent. A signal indicating the voltage across the sense resistorR_(sense) which represents the coil current is fed back to a comparator64 for comparison with the required current I_(req).

The operation of the circuit 60 is shown in the graph of FIG. 7. Asignal to trigger the switch between bottom and top sensing is labelledDCB. As shown in the graph this signal DCB is switched when aninstability is detected in the form of a state: “required current is notreached −no switching event in this PWM period detected”. This canhappen if the back emf B_(emf) increases to greater than 50% of batteryvoltage +Bat for top sensing. The graph also shows it happening if theback emf B_(emf) drops below 50% of battery voltage+Bat for bottomsensing. In either case, the DCB signal causes a switch between bottomand top sensing to make sure that the duty cycle is maintainedconsistently between 0% and 100%. Without this automatic selectionbetween top and bottom sensing, when duty cycles are reaching 50%, thePWM duty cycle would oscillate over different PWM periods between twostates: (a) values different from 0% and 100% and (b) values equal to100% or equal to 0%. This effect is also visible in FIG. 7, indicated bythe arrows “instability detected”. The top-bottom sensing selectionlimits the duration of this instability to the periods of detection.

The controller output is provided by an SRS latch 65. An MS input of thelatch 65 is driven by the DCB signal ANDed with the clock signal Clk. AnR input of the latch 65 is driven by either the clock signal Clk, or thecomparator output CMP, depending on the DCB level. An SS input of thelatch 65 is driven by a NOR of the DCB signal and the comparator outputCMP.

The graph of FIG. 7 starts with back emf B_(emf) lower than half thebattery voltage, and with top sensing. When the back emf B_(emf)increases, the PWM duty cycle of the controller output Out increases.When the duty cycle is going above 50%, then I_(req) is not reachedwithin the period (i.e. duty cycle is one period 100%), so the DCBsignal goes low and bottom sensing starts. The duty cycle then furtherincreases. When the back emf B_(emf) drops, the duty cycle decreases to50%, and below 50% again I_(req) is not reached within the period (i.e.duty cycle is one period 0%), then the DCB signal goes high. Top sensingresumes and the duty-cycle can further decrease below 50% withoutoscillations.

Applications and Concluding Remarks

Embodiments of the invention are applicable to:

-   -   Any sort of full bridge drive    -   Any sort of inductive load    -   Any sort of current sensing in coils

Advantages include:

-   -   Full control of PWM frequency. This can have a variety of        benefits such as reduction of audible noise possible by        designing PWM frequency above 20 kHz independent of system        parameters or their variations. Also there is better control        over thermal effects related to dissipation during PWM        switching.    -   Full current control 0% to 100% of PWM duty cycle is possible.    -   Compact solution: no mixed decay mode, only one decay mode per        period.    -   It can be implemented with simple logic gates, no need for        complexity and cost of a microprocessor or complex logic. It can        be easily formed in an integrated circuit, or as a system with        its associated load such as a motor or motors, and other parts        such as parts being moved by the motor. Thus it can be made more        reliable for rugged environments such as automotive electronics        and can be cost effective.

It is useful for controlling any sort of electric motors, particularlyin stepper motor drivers. It could increase acceptance of the steppermotor driver products because of improved audible noise. Especially inautomotive HVAC (heating ventilation and air conditioning) market, thisis highly desired as the actuator flaps are in contact with the air-flowthat is transported in the passenger compartment. The PWM controllersdescribed can also be used in conjunction with other inductive loads.

As has been described, a PWM controller for a bridge driver circuit forcontrolling current in an inductive load such as a motor, can set thedriver into a forward mode, a slow decay mode or a fast decay mode, andcan switch from slow decay mode into forward mode or into fast decaymode for the duration of pulses at a controlled frequency to providepulse width modulated control of the current. This is a simpler controlscheme avoiding complex switching schemes related to mixed mode decay.By using a known frequency, it is easier to avoid the problems ofvariable frequency such as increased heat dissipation or acoustic noisegeneration. It can have a selector for selecting top or bottom senseswitching, avoiding duty-cycle oscillations and enabling a wider rangeof PWM duty-cycles to be used (e.g. 0% to 100%), which is useful tocompensate for Back emf influence on coil-drive.

1. A controller for a bridge driver circuit for controlling current inan inductive load, the controller including one single pulse widthmodulator and one single current sensor providing feedback to thecontroller, the controller being arranged to set the driver into aforward mode, a slow decay mode or a fast decay mode, and being arrangedto switch from slow decay mode into forward mode or into fast decay modeat controlled time intervals to provide pulse width modulated control ofthe current whereby both, the switching into said forward mode and theswitching into said fast decay mode is done under the control of saidsingle pulse width modulator.
 2. The controller of claim 1 having aselector for selecting top or bottom sense switching.
 3. The controllerof claim 2, the selector being arranged to select according to a dutycycle of an output of the controller.
 4. The controller of claim 3,having a detector for detecting when the duty cycle reaches apre-determined value between 0.5 and 1, and using this to make theselection.
 5. The controller of claim 1, having a latch for outputting adrive control signal, the latch being set by a clock signal and reset bya signal indicating a current in the inductive load has reached adesired level.
 6. The controller of claim 1, arranged to delay aswitching of the bridge driver to provide a guard band to avoid anoverlap between modes.
 7. A pulse width modulation controller forcontrolling current in an inductive load, according to a comparison of adesired and a measured current, the controller including only one singlepulse width modulator, the controller being arranged to carry out topsensing where for each pulse the current is driven up until it reachesthe desired value, then allowed to decay, or to carry out a bottomsensing where for each pulse the current is driven away from the desiredvalue and allowed to decay towards the desired value, the controllerhaving a selector for selecting top or bottom sense switching.
 8. Thecontroller of claim 7, the selector being arranged to select accordingto a duty cycle of an output of the controller.
 9. An integrated circuitcomprising: a controller for a bridge driver circuit for controllingcurrent in an inductive load, the controller including one single pulsewidth modulator and one single current sensor providing feedback to thecontroller, the controller being arranged to set the driver into aforward mode, a slow decay mode or a fast decay mode, and being arrangedto switch from slow decay mode into forward mode or into fast decay modeat controlled time intervals to provide pulse width modulated control ofthe current.
 10. An integrated circuit comprising: a pulse widthmodulation controller for controlling current in an inductive load,according to a comparison of a desired and a measured current, thecontroller including only one single pulse width modulator, thecontroller being arranged to carry out top sensing where for each pulsethe current is driven up until it reaches the desired value, thenallowed to decay, or to carry out a bottom sensing where for each pulsethe current is driven away from the desired value and allowed to decaytowards the desired value, the controller having a selector forselecting top or bottom sense switching.
 11. A system comprising: amotor; and a controller for a bridge driver circuit for controllingcurrent in the motor, the controller including one single pulse widthmodulator and one single current sensor providing feedback to thecontroller, the controller being arranged to set the driver into aforward mode, a slow decay mode or a fast decay mode, and being arrangedto switch from slow decay mode into forward mode or into fast decay modeat controlled time intervals to provide pulse width modulated control ofthe current whereby both, the switching into said forward mode and theswitching into said fast decay mode is done under the control of saidsingle pulse width modulator.
 12. A system comprising: a motor; and apulse width modulation controller for controlling current in the motor,according to a comparison of a desired and a measured current, thecontroller including only one single pulse width modulator, thecontroller being arranged to carry out top sensing where for each pulsethe current is driven up until it reaches the desired value, thenallowed to decay, or to carry out a bottom sensing where for each pulsethe current is driven away from the desired value and allowed to decaytowards the desired value, the controller having a selector forselecting top or bottom sense switching.
 13. A method of controlling acurrent in an inductive load by switching between a forward mode, a slowdecay mode or a fast decay mode, the method having the act of switchingfrom slow decay mode into forward mode or into fast decay mode for theduration of pulses at controlled time intervals to provide pulse widthmodulated control of the current whereby a single pulse width modulatoris controlling the time and duration of said pulses at controlled timeintervals for said switching into forward mode and for said switchinginto fast decay mode.
 14. The method of claim 13, further comprisingselecting top or bottom sense switching.
 15. The method of claim 14,wherein the selection is made according to a duty cycle of an output ofthe controller.
 16. The method of claim 15, further comprising detectingwhen the duty cycle reaches a pre-determined value between 0.5 and 1,and using this to make the selection.
 17. The method of claim 13,further comprising sensing a current in the inductive load to providefeedback control.
 18. The method of claim 13, further comprisingoutputting a drive control signal which is set by a clock signal andreset by a signal indicating a current in the inductive load has reacheda desired level.
 19. The method of claim 13, further comprising delayinga switching to provide a guard band to avoid an overlap between modes.20. A method of controlling a current in an inductive load by pulsewidth modulation according to a comparison of a desired and a measuredcurrent, the measured current being delivered by one single currentsensor and the pulse width modulation obtained from one single pulsewidth modulator, the method having the act of selecting between topsensing where for each pulse the current is driven up until it reachesthe desired value, then allowed to decay, or bottom sensing where foreach pulse the current is driven away from the desired value and allowedto decay towards the desired value.
 21. The method of claim 20, whereinthe selecting is arranged according to a duty cycle or an output of acontroller.